1. Field of the Invention
The present invention relates to data receiving techniques in a high-speed data transmission system. In particular, the invention relates to a high-speed data receiving circuit and method allowing reliable data reception even when a received clock signal and/or the received data vary in phase.
2. Description of the Prior Art
In Japanese Patent Application Unexamined Publication No. 10-247903, a bit-sync circuit has been disclosed in which the phase of received data is compared with the phases of multiple clock signals generated from a system clock signal and a clock signal having a phase to be used for data capturing is selected from the multiple clock signals depending on a comparison result.
More specifically, the above conventional circuit in the case of 4-phase clock signals as describe din the Publication No. 10-247903 will be described referring to FIG. 8.
As shown in FIG. 8, this conventional example is composed of the following circuits. Delay circuits 101a-101c receive a system clock signal and generates multiple clock signals by delaying the system clock signal by different delay times. A phase comparison pulse generator 102 inputs received data and 4-phase clock signals (that is, the system clock signal and the clock signals obtained by the delay circuits 101a-101c), and generates a received data phase signal and clock phase signals, which have a constant pulse width, based on leading-edges and trailing-edges of the received data and leading-edges of the system clock signal and the multiple clock signals obtained by the delay circuits 101a-101c.
A phase selector 103 selects one of the clock phase signals output from the phase comparison pulse generator 102 in accordance with a received phase selection signal SEL. A clock selector 104 selects one of the system clock signal and the multiple clock signals that are output from the delay circuits 101a-101c in accordance with a received phase selection signal SEL. A phase comparator 105 compares the phase of the received data phase signal output from the phase comparison pulse generator 102 and the phase of the selected clock phase signal output from the phase selector 103.
A phase decision circuit 106, which is an up/down counter, generates a phase selection signal SEL to be output to the phase selector 103 and the clock selector 104 depending on a comparison result of the phase comparator 105. A latch circuit 107 latches the received data according to the clock signal selected by the clock selector 104. The selected clock signal is output as an output clock signal.
In the above conventional circuit, the phase comparator 105 compares the phase of the received data phase signal and the phase of a selected clock phase signal that is selected by the phase selector 103. A comparison result of the phase comparator 105 is output to the phase decision circuit 106.
If the comparison result indicates a possibility that the received data phase signal and the selected clock phase signal do not provide a sufficient setup time, then the phase decision circuit 106 generates a phase selection signal SEL that causes the phase of a clock signal selected by the phase selector 103 to be delayed so as to increase the setup time.
If the comparison result indicates a possibility that the received data phase signal and the selected clock phase signal do not provide a sufficient hold time, then the phase decision circuit 106 generates a phase selection signal SEL that causes the phase of a clock signal selected by the phase selector 103 to be advanced so as to increase the hold time.
If the comparison result indicates that the received data phase signal and the selected clock phase signal satisfy both of sufficient setup time and hold time, the phase decision circuit 106 generates a phase selection signal SEL that causes the phase of a clock signal selected by the phase selector 103 to be kept. The phase selection signal SEL thus generated is output to the phase selector 103 and the clock selector 104.
The clock selector 104 selects one of the system clock signal and the multiple clock signals obtained by the delay circuits 101a-101c depending on the phase selection signal SEL, and outputs it as an output clock signal.
The clock signal that is output as the output clock signal from the clock selector 104 is also input to the latch circuit 107. The latch circuit 107 captures the received data according to the finally selected clock signal, and outputs the resulting data as output data.
However, in the above conventional circuit, the received data actually latched by the latch circuit 107 takes a different route than the received data phase signal that reaches the phase comparator 105 via the phase comparison pulse generator 102 for clock phase adjustment. A clock signal that is actually selected by the clock selector 104 also takes a different route than a selected clock phase signal that reaches the phase comparator 105 via the phase comparison pulse generator 102 and the phase selector 103.
A combination of delays in these four routes may cause the reduced reliability of the comparison result obtained by the phase comparator 105. More specifically, even if a comparison result of the phase comparator 105 indicates that both of the setup time and the hold time are satisfied, a clock signal selected by the clock selector 104 does not necessarily satisfy both of the setup time and the hold time when the latch circuit 107 captures received data. This causes a problem such that correct data may not be captured.
For example, consider the case that the delay in the clock selector 104 is a half of one clock cycle and the delays in the circuits other than the clock selector 104 are zero.
In this case, although a phase comparison result of the phase comparator 105 indicates that the phase of the change points of received data and the phase of leading-edges of the clock signal are deviated from each other by only a half of one clock cycle, the phase of the received data input to the latch circuit 107 comes to coincide with the phase of the clock signal input to the latch circuit 107 when the clock signal is delayed in the clock selector 104 by a half of one clock cycle. Actually, since neither the setup time nor the hold time is satisfied, it is impossible to capture correct data.
To avoid such a problem, it is necessary to adjust delays in the circuits and interconnections from branching points 108 and 109 to the latch circuit 107 and the phase comparator 105.
Such adjustments are easy in the case where the frequency of received data is low. However, there is a problem that, as the frequency of received data increases, the delays need to be adjusted so as to fall within a small range and therefore the circuit implementation becomes more difficult.